- Give two ways of converting a two input NAND gate to an inverter
- Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
- What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
- Give a circuit to divide frequency of clock cycle by two
- Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
- Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)
- The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?
- What are the different Adder circuits you studied?
- Give the truth table for a Half Adder. Give a gate level implementation of the same.
- Draw a Transmission Gate-based D-Latch.
- Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
- How do you detect if two 8-bit signals are same?
- How do you detect a sequence of "1101" arriving serially from a signal line?
- Design any FSM in VHDL or Verilog.
- Explain RC circuit.s charging and discharging.
- Explain the working of a binary counter.
- Describe how you would reverse a singly linked list.

### Hardware designing interview Questions

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