Verilog Interview Questions,Faqs

Verilog Interview Questions
Q: What is the difference between a Verilog task and a Verilog function?
Q: Given the following Verilog code, what value of "a" is displayed?
always @(clk) begin
a = 0;
a <= 1; $display(a); end Q: Given the following snipet of Verilog code, draw out the waveforms for "clk" and "a".
always @(clk) begin
a = 0;
#5 a = 1;
end
Q: What is the difference between the following two lines of Verilog code?
#5 a = b; a = #5 b;
Q: Write the Verilog code to provide a divide-by-3 clock from the standard clock.
Q: What is the difference between:
c = foo ? a : b;
and
if (foo) c = a; else c = b;

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